1. Field of the Invention
This invention relates to Class-D amplifier circuits, especially to Pulse-Width-Modulated or Sigma-Delta Class-D amplifiers, with circuitry for reducing power consumption, and in particular to Class-D audio amplifiers.
2. Description of the Related Art
FIG. 1 shows a basic arrangement of one example of a pulse-width-modulated (PWM) Class-D amplifier 100, sometimes referred to as a Sigma-Delta amplifier or switch-mode amplifier. An output stage 101 comprises at least two switches connected in series between two supplies, which may be, for example, a unipolar supply voltage Vdd and ground (GND) or could be bipolar positive and negative supply voltages.
The output node at the common node of the two series switches is switched between the power supplies to provide a rail-to-rail square wave output with a duty cycle controlled to provide the desired output voltage. In some embodiments the output stage may be connected to a passive reactive smoothing filter 102 to provide low pass filtering of the output signal VOUT to a load 103. In some embodiments however the filter arrangement 102 may be omitted and the load 103 connected directly to the output stage, relying on inherent filtering in the load 103 itself.
The output stage 101 is controlled by a modulator 104 which receives the input signal SIN to be amplified and derives control signals for switching the output stage 101 in an appropriate switching cycle. In a PWM amplifier the output voltage may be fed back and compared/combined with the input signal SIN to derive an error signal. This error signal is passed through a loop filter 106 and then typically compared, by comparator 105, to a reference waveform to control the duty cycle of the output stage. Typically the reference waveform is a repeating ramped waveform such as a triangular or sawtooth type waveform. To provide the reference waveform a waveform generator 107 may receive a clock signal FIN at a switching frequency fSW which defines the ramp period. This clock signal FIN may also be used to reset the comparator 106. In such an arrangement the switching frequency fSW defines the overall switching cycle frequency of the output stage 101.
Such Class-D amplifiers can be ideally 100% efficient as the output is rail-to-rail and the filter 102, if present, contains only reactive components. In practice however there will be power losses, for example due to power consumption of the control circuitry, ohmic (I2R) losses associated with the non-zero resistance of the switch elements and power consumed in driving the control nodes of the switch devices. There may also be losses due to any overlap in on-time of the practical switches allowing shoot through current or underlap, i.e. excessive deadtime, when both switches are off and recirculating inductive current flows through a body diode associated with a switch with a diode drop loss.
It will of course be appreciated that FIG. 1 illustrates only one example of a fairly simple arrangement and other more complex arrangements exist however the basic principles described apply generally to Class-D type amplifiers.
It would be desirable, especially for Class-D amplifiers used in battery powered devices such as portable electronic devices, to reduce power losses where possible.